Printed circuit boards are used in many electronic devices for purposes of routing signals between electrical and electronic components that are (1) mounted on the PCB, (2) connected to the PCB via edge connectors, or (3) fabricated directly into the PCB. PCBs generally are flat square or rectangular boards primarily formed of a dielectric material with copper or other conductive traces formed therein to route signals between the various aforementioned electronic components. The term circuitry shall be used herein to refer broadly to any form of electrical or electronic components, including analog components, digital components, ground planes, and simple conductors such as copper traces.
A PCB has two opposing external major surfaces, one or both of which may bear circuitry. In addition, multilayer PCBs are well known in which one or more layers of circuitry are disposed in between the two opposing external major surfaces. Vias are commonly used to connect signals on any one of these layers to any other one of these layers. A via essentially is a hole that is drilled or otherwise formed in the PCB between any two layers and plated or filled with copper or another conductor. Due to ease of fabrication issues, vias typically are drilled completely through the PCB even if the via is used to connect circuitry on two internal layers or one of the two external layers (topmost layer or bottommost layer) and an internal layer.
“Backplane” is the common terminology used for specific type of PCB found in many electronic devices, such as computers, that is usually large in size (e.g., greater than about 9 inches per edge) and that contains connectors on the edge of the PCB into which additional electronic components may be plugged, such as computer peripheral cards (often called plug-in cards).
Commonly, the edge connectors on the PCB for connecting a plug-in card or other electronic component or device are installed on the surface or edge of the PCB and connected to signals on other layers with vias. Specifically, one common method is to install a connector comprising a conductive pin that extends into the via hole from one of the external major surfaces of the PCB that makes electrical contact with the metalized wall of the via. These metal pins are called press-fit pins and rely on mechanical forces to ensure electrical connection.
Vias generally comprise a change point in signal flow that tends to cause a great deal of signal degradation, particularly with respect to signals in the radio and microwave frequency range, and more specifically signals having frequencies over 100 MHz. Vias generally look like a capacitance to high frequency signals passing therethrough. A copper trace on a PCB typically has an impedance of 50 for a single ended trace or 100 ohms for differential signals, whereas a via typically has a much lower impedance, that impedance being primarily capacitive. Typically, the longer the via, the greater the capacitance and, therefore, the greater the signal degradation. This problem is particularly acute with respect to vias used for connectors because such vias must have a certain close spacing (usually standardized) in order to properly mate with the connector pins of a plug-in card. Also, the backplanes on which such connector vias are commonly found tend to be rather thick PCBs because they commonly must accommodate a large number of layers due to the need to route a large number of signals over the PCB.
Accordingly, it is common practice in PCB fabrication to drill vias completely through the PCB, plate the entire via with copper or another conductive material, and then counterbore the vias to remove the unnecessary copper therein. The unnecessary copper in any given via is the copper that runs between any layers of the PCB that are not being electrically interconnected by that via. For instance, if a particular via is provided to interconnect the topmost external layer with the second topmost, internal layer of the PCB, then the via would be counterbored from the bottommost external layer up to but just short of the second topmost layer.
For instance, FIGS. 1A and 1B show a conventional via before and after counterboring. In these Figures, the actual PCB dielectric material is not shown for sake of clarity. However, it will be understood that the spaces between the conductive layers are occupied by the PCB dielectric material. In this example, the via 101 is a copper plated hollow tube running the entire depth of the PCB. This PCB has five conductive layers, namely, top external layer 103, bottom external layer 105, a first ground plane layer 107, a second ground plane layer 109 and a signal layer 111 sandwiched between the two ground plane layers 107, 109. The ground plane layers 107 and 109 generally are each essentially complete sheets of copper 108, 110, respectively, that substantially occupy the entire layer except for areas 121, 123 immediately surrounding the vias since, generally, each via forms part of a signal path between two electronic components and, therefore should not be shorted to ground. These areas around the vias that do not comprise copper are commonly called anti-pads 121, 123. On the top and bottom layers 103 and 105 and any signal layer, such as signal layer 111, to which the via 101 is to make a connection, a copper pad is formed around and in contact with the copper plating of the via. See, for instance, top pad 113, bottom pad 115 and signal layer pad 117. A signal trace 119 connects to the signal layer pad 117 for carrying a signal and/or from the via 101 between the two (or more) electronic components that are to be connected using the via as part of the signal path therebetween,
In theory, signal lines like trace 119, can run right up to the via 101 and the pads 113, 115, 117 can be eliminated. However, the use of pads such as pads 113, 115, and 117 allows for lower manufacturing tolerances in terms of at least, position of the via and the signal traces. In this example, the via is to a connector that is to connect a signal placed on the top pad 113 by connecting a press fit pin of the connector to the signal path 119 in the signal layer 111.
After the via is fully formed as shown in FIG. 1A, the via is counterbored by drilling with a drill having a larger diameter than the via 101 from the bottom surface 105 up to, but just short of, the signal layer 111. The shaded cylinder 125 in FIG. 1B represents the portion of the via and PCB that is removed by the counterboring drill. As can be seen, this counterboring eliminates almost all of the copper in the via between the bottom layer 105 and the signal layer 111, all of which is unnecessary for purposes of connecting the top pad 113 to the signal trace 119 in the signal layer 111. However, there is some copper left below signal layer 111 simply because the drilling can be performed only to certain practical tolerances and, therefore, room for such tolerance errors must be designed into the drilling operation to assure that the drill does not inadvertently drill into the signal layer 111, which would break the desired signal path from the top pad 113 of the via to the signal path 119 in signal layer 111. On the other hand, if the drill does not drill far enough, then more copper will remain in the via than is necessary, leading to increased signal degradation.
It can readily be detected if the drill drills too far by simple resistive testing. Specifically, an ohmmeter can be placed across the top pad 113 and the destination of signal trace 119. If an open circuit is detected, the pad 117 has been breached and the PCB is defective. However, there is no easy way to determine if the drill did not drill as deeply as desired (so that the signal degradation caused by the via is greater than it needs to be). While there are ways to determine if the counterbore has not been drilled deep enough, they are not practical for standard PCB testing. For instance, the depth of the counterbore can be determined visually by observation with a microscope. However, this is not a solution that can be reasonably implemented on a production scale because of the labor and cost involved. It also is possible to test the via by placing a high frequency signal across the via and testing the output for signal degradation. However, this also is a time consuming and expensive proposition that is not reasonable to implement on a production scale.